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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
INTRODUCTION
48-LQFP-0707 The S1T8536 is a single chip RF transceiver optimized for use in ISM 2.45GHz wireless systems. It is fabricated using Samsung's ASP5HB 0.5um advanced BiCMOS process. The S1T8536 contains receiver, transmitter, frequency doubler, voltage controlled oscillator (VCO), phase locked loop(PLL) and crystal oscillator. The receiver consists of a 2.4 - 2.5GHz high frequency mixer, an intermediate frequency (IF) amplifier, a FM quadrature demodulator, a received signal strength indicator (RSSI), a baseband filter buffer amplifier and a high speed data slicer with sample & hold function. The transmitter consists of 2.4 - 2.5GHz high frequency buffer amplifier. The PLL operates upto 1.3GHz with 32/33 prescaler and selectable charge pump current. S1T8536 contains onchip PLL regulator to minimize switching noise. The VCO operates 1.15 - 1.3GHz and requires only external tank circuit and loop filter. S1T8536 contains on-chip VCO regulator to minimize VCO frequency variation due to supply pushing. The frequency doubler receives 1.15 - 1.3GHz signal from VCO and outputs 2.3 - 2.6GHz signal to receiver and transmitter. The crystal oscillator operates 5 - 40MHz and can accept external clock signal. Two additional voltage regulators provide a stable supply source to external discrete stages in the Rx and Tx chains.
FEATURES
* * * * * * * * * 2.4GHz - 2.5GHz Single-Chip RF Transceiver Samsung ASP5HB 0.5um Advanced BiCMOS Process 3.0V to 5.5V Operation (RX / TX mode supply current of 75mA / 50mA) Single Conversion Receiver with 110MHz IF Frequency Quadrature Demodulator with Greater than 1MHz Bandwidth Wideband Buffer Amplifier for Baseband Filtering High Speed Data Slicer Operating Upto 2Mbps with Sample & Hold 1.3GHz PLL with VCO and Frequency Doubler PLL, VCO, RX and TX Voltage Regulator Included (2.85V)
APPLICATION
* 2.45GHz ISM Band Wireless Communication Systems
ORDERING INFORMATION
Device S1T8536X01-T0R0 Package 48-LQFP-0707 Operating Temperature - 10 to + 70C
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S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
BLOCK DIAGRAM
MOP
36
MON
35
VCC MIX
34
VCC MIX
33
VCC IF
32
IFP
31
IFN
30
GND IF
29
GND IF
28
GND VCC QUAD QUAD QUAD IN
27 26 25
VREG 37 RX GND 38 MIX GND 39 MIX MIP 40 MIN 41 GND 42 FD VREG 43 TX GND 44 FD VCC 45 FD TX OUT 46 GND 47 VCO VCC VCO 48 Regulator (2.85V)
1 2
Regulator (2.85V)
A
24
GND BB QUAD OUT BUF IN BUF OUT DS INP DS INN
23
RSSI
1
22
21
20
Frequency Doubler Sample Hold Regulator (2.85V) RF Counter
19
18 SHO 17 DS OUT 16 SHEN
PFD
REF Counter
15 RSSI
CONTROL
14 CE 13 OSCI
Regulator (2.85V)
Charge Pump
Lock Detector
3
4
5
6
7
8
9
10
11
12
VREG VCOP VCON VCO
GND PLL
VCC PLL
VREG PLL
CP
LD
CLK DATA
LE
OSCO
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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
PIN CONFIGURATION
MOP MON
36 35
VCC VCC MIX MIX
34 33
VCC IF
32
IFP
31
IFN
30
GND GND GND VCC QUAD IF IF QUAD QUAD IN
29 28 27 26 25
VREG 37 RX GND 38 MIX GND 39 MIX MIP 40 MIN 41 GND 42 FD VREG 43 TX GND 44 FD VCC 45 FD TX OUT 46 GND 47 VCO VCC VCO 48
1 2 3 4 5 6 7 8 9 10 11 12
24
GND BB QUAD OUT BUF IN BUF OUT DS INP DS INN
23
22
21
20
S1T8536
19
18 SHO 17 DS OUT 16 SHEN
15 RSSI 14 CE 13 OSCI
VREG VCOP VCON GND VCC VREG VCO PLL PLL PLL
CP
LD
CLK DATA
LE
OSCO
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S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PIN DESCRIPTION
Pin 1 Name VREGVCO
VCCVCO
Schematic
Description VCO regulator output (2.85V). Requires external bypass capacitor.
1
2 3
VCOP VCON
2
3
These differential ports are used to supply DC voltage to the VCO as well as tune the center frequency of the VCO.
4 5 6
GNDPLL VCCPLL VREGPLL
VCCPLL
Ground of PLL section (Note 1). Supply of PLL section. PLL regulator output (2.85V). Requires external bypass capacitor.
6
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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
PIN DESCRIPTION (Continued)
Pin 7 Name CP
VCCPLL
Schematic
Description Charge pump output.
7
8
LD
8
Lock detector open drain output.
9 10 11
CLK DATA LE
9, 10, 11
VCCPLL
Programming clock input. Programming data input. Programming load enable input.
12 13
OSCO OSCI
VREGPLL(2.85V)
Crystal oscillator input. Crystal oscillator output.
13
12
14
CE
VCCPLL
14
Chip enable input. Logic high input enables the chip and logic low input disables the chip.
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S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PIN DESCRIPTION (Continued)
Pin 15 Name RSSI
VCCIF
Schematic
Description Received signal strength indicator output.
15
16
SHEN
VCCIF 16
Sample and hold enable input. High signal input enable sample and hold function and low signal input disable sample and hold function .
17
DSOUT
VCCIF 17
Data slicer output.
18
SHO
Sample and hold output.
18
19 20
DSINN DSINP
19
VCCIF
Data slicer negative input. Data slicer positive input.
20
21 22
BUFOUT BUFIN
VCCIF
Baseband filter buffer amplifier output. Baseband filter buffer amplifier input.
22
21
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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
PIN DESCRIPTION (Continued)
Pin 23 Name QUADOUT
VCCQUAD
Schematic
Description Quadrature demodulator output.
23
24 25
GNDBB QUADIN
VCCQUAD 25
Ground of baseband section (Note 1). Quadrature demodulator tank input.
26 27 28 29 30 31
VCCQUAD GNDQUAD GNDIF GNDIF IFN IFP
Supply of quadrature detector section. Ground of quadrature detector section (Note 1). Ground of IF amplifier section (Note 1). Pin28 and Pin29 are connected internally. IF amplifier differential inputs. DC blocking is required.
VCCIF
30 31
32 33 34
VCCIF VCCMIX VCCMIX
Supply of IF amplifier section. Supply of mixer section. Pin33 and Pin34 are connected internally.
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S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PIN DESCRIPTION (Continued)
Pin 35 36 Name MON MOP Schematic Description RF mixer differential IF outputs.
VCCMIX
35
36
37
VREGRX
VCCMIX
RX regulator output (2.85V). Requires external bypass capacitor.
37
38 39 40 41
GNDMIX GNDMIX MIP MIN
Ground of mixer section (Note 1). Pin38 and Pin39 are connected internally. RF mixer differential inputs. DC blocking is required.
VCCMIX
40 41
42
GNDFD
Ground of frequency doubler section (Note 1).
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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
PIN DESCRIPTION (Continued)
Pin 43 Name VREGTX
VCCFD
Schematic
Description TX regulator output (2.85V). Requires external bypass capacitor.
43
44 45 46
GNDFD VCCFD TXOUT
VCCFD
Ground of frequency doubler section (Note 1). Supply of frequency doubler section. TX buffer amplifier output.
46
47 48
NOTE:
GNDVCO VCCVCO
Ground of VCO section (Note 1). Supply of VCO section.
All ground pads of the chip are down bonded to package ground paddle and each ground pin of the IC is connected to that package ground paddle. So all the ground pins are connected together through the exposed ground paddle of the IC package. Proper connection of package ground to board ground is essential and highly required.
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S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
ABSOLUTE MAXIMUM RATINGS
Characteristics Power Supply Voltage Voltage applied to any pin Storage Temperature Range Symbol VCC VIN TSTG Value 6.0 VCC + 0.3 -65 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS
Characteristics Power Supply Voltage Operating Temperature Symbol VCC Ta Value 3.6 -10 to +70 Unit V C
Caution : S1T8536 is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device should be done at ESD work stations.
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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
DC ELECTRICAL CHARACTERISTICS
(Ta = 25C, VCC = 3.6V, unless otherwise noted.) Characteristics RX Mode Supply Current (Receiver + Frequency Doubler + PLL + VCO) TX Mode Supply Current (Transmitter+Frequency Doubler+PLL+VCO) Locking Mode Supply Current (PLL + VCO) Power Down Mode Supply Current (All Off) Symbol ICC-RX ICC-TX ICCLOCK ICC-PD Test condition CE(PIN14)=LOW Min Typ 75 50 20 10 Max 100 70 30 100 Unit mA mA mA uA
RECEIVER / TRANSMITTER ELECTRICAL CHARACTERISTICS (Ta=25C, VCC=3.6V, unless otherwise noted. RF=2.45GHz/-47dBm, LO=1.17GHz/-15dBm, IF=110.592MHz Data = 1Mbps pseudo random sequence with BTb = 0.5 GFSK modulation. Modulation index = 0.5) Characteristics Mixer Input RF Frequency Mixer Output IF Frequency 1E-3 BER Sensitivity (Notes 1 and 2) IF Amplifier Bandwidth IF Amplifier Voltage Gain Quadrature Demodulator Output Voltage Quadrature Demodulator Bandwidth Baseband Filter Buffer Amplifier Bandwidth Baseband Filter Buffer Amplifier Voltage Gain Data Slicer Maximum Operating Frequency RSSI Dynamic Range (110MHz IF Amp Input) RSSI Output Level (110MHz IF Amp Input) TX Output Power (Notes 1 and 2) Symbol RF In Freq. IF Out Freq SENS IFAmp BW IFAmp Gain DET Out DET BW BB Amp BW BB Amp Gain DS BW RSSI DR RSSI Out TX Out Test condition 50ohm matching SAW matching data out External load variable External load variable IF input(110MHz) 50ohm matching Min 2.4 50 50 70 100 0.6 1 -3 1 50 0.5 Typ 110.6
Max 2.5 200 -76 200 200 +3 2.0 -
Unit GHz MHz dBm MHz dB mVrms MHz MHz dB Mbps dB V dBm
-82 75 150 1 2 0 2 60 -15
NOTES: 1. Not 100% AC tested but guaranteed by design and characterization. 2. Measured result on evaluation board with proper impedance matching.
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S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
VCO / PLL ELECTRICAL CHARACTERISTICS (Ta = 25C, VCC = 3.6V, unless otherwise noted) Characteristics VCO Operating Frequency (Note 1) PLL Operating Frequency PLL Input Sensitivity (external VCO Input) OSC Operating Frequency OSC Input Sensitivity Charge Pump Output Current Symbol VCO Freq. RF In Freq RF In Power OSC In Freq. OSC In Power CPI = Low CPI = High Test condition Min 1150 1150 -15 5 100 1.1 2.1 Typ 500 1.5 3.0 Max 1300 1300 5 40 2000 2.0 4.0 Unit MHz MHz dBm MHz mVpp mA mA
NOTE: Not 100% AC tested but guaranteed by design and characterization.
REGULATOR ELECTRICAL CHARACTERISTICS (Ta = 25C, VCC = 3.6V, unless otherwise noted.) Characteristics PLL Regulator Voltage (Note 1) VCO Regulator Voltage (Note 1) RX Regulator Voltage (Notes 1 and 2) TX Regulator Voltage (Notes 1 and 2) Symbol VREG-PLL VREG-VCO VREG-RX VREG-TX Test condition load regulated load regulated load regulated load regulated Min 2.7 2.7 2.7 2.7 Typ 2.85 2.85 2.85 2.85 Max 3.0 3.0 3.0 3.0 Unit V V V V
NOTES: 1. Voltage regulation operates under the condition of supply voltage greater than 3.3V. 2. RX and TX regulator are tested with load current of 10mA.
DIGITAL I / O ELECTRICAL CHARACTERISTICS (Ta = 25C, VCC = 3.6V, unless otherwise noted) Characteristics High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Symbol VIH VIL VOH VOL Test condition Min VCC-0.4 0 VCC-0.4 0 Typ Max VCC 0.4 VCC 0.4 Unit V V V V
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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
RECEIVER FUNCTIONAL DESCRIPTION General The S1T8536's receiver is a single conversion wideband FM / FSK receiver. This device is designed for use as the receiver in analog and digital FM systems such as 2.4GHz ISM band cordless phones and wideband data links with data rates up to 2Mbps. It contains high frequency mixer, IF amplifier, quadrature detector, baseband filter amplifier and data slicer with sample and hold function. Mixer The mixer is a double-balanced with fully differential RF inputs and fully differential IF outputs. Following figure shows the external components required for wideband 110.592MHz IF operation.
MOP MON
36 36
IFP
31
IFN
30
110.592MHz SAW VCC
Quadrature Demodulator The quadrature demodulator requires tank circuit with loaded Q depending on detection bandwidth. Following figure shows external components required for 110.592 MHz IF operation.
QUAD IN
25
QUAD OUT
23
10pF
56nH
VCC
22pF
Baseband Filter Buffer Amplifier Baseband filter amplifier is a wideband buffer and it can be configured as a second-order sallen-key low pass filter. Following figure shows the external components required. Cutoff frequency = 1 / [2*SQRT(R1R2C1C2)] Quality factor = SQRT(R1R2C1C2) / (R1C2 + R2C2) The component value of R1 should contain the quadrature detector output resistance.
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S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
RECEIVER FUNCTIONAL DESCRIPTION
C1 Vout C2 R2
21 22
R1
Vin
BUF OUT
BUF IN
Data Slicer with Sample and Hold The data slicer is a comparator that is designed to square up the data signal. The recovered data signal from the baseband filter output can be DC coupled to the data slicer DS-INP(Pin 20). The S1T8536's data slicer incorporates an sample and hold used to derive the data slicer reference voltage by means of an external integration circuit. The sample and hold is 'ON' during reception of the preamble data pattern, and is otherwise `OFF' in TDD (Time Division Duplex) system. The external integration circuit is formed by an RC low pass circuit placed between SHO (Pin 18) and ground. The size of this resistor and capacitor and the nature of the data signal determine how faithfully the data slicer shapes up the recovered signal. The time constant is short for large peak to peak voltage swings or when there is a change in DC level at the detector output. For small signal or for continuous bits of the same polarity which drift close to the threshold voltage, the time constant is longer. The sample and hold is able to sink/source 3mA to/from the external integration circuit in order to minimize the settling time. When the sample and hold is `OFF' the output (SHO) is in high impedance state with extremely low leakage current. Following figure shows the internal block diagram.
DS INP 20
17 DS OUT
DS INN 19 SHO 18 SHEN 16
+1
The output of the data slicer (DS-OUT) is a CMOS compatible bitstream. However, it is recommended that an external NPN amplifier stage be used to drive the CMOS baseband processor, in order to minimize the amount of ground and supply currents in the S1T8536 which might desensitize the chip.
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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
PLL / VCO FUNCTIONAL DESCRIPTION GENERAL The S1T8536's PLL / VCO is a high performance frequency synthesizer with high frequency voltage controlled oscillator and integrated high frequency prescalers for RF operation upto 1.3GHz. It contains two voltage regulator of VCO and PLL, dual modulus prescalers providing 32/33 division, no dead-zone PFD, selectable charge pump current, lock detector output and crystal oscillator. VCO / PLL VOLTAGE REGULATOR The S1T8536's PLL / VCO incorporates one on-chip 2.85V voltage regulators for stable VCO operation and another on-chip 2.85V voltage regulators for minimizing ECL and CMOS switching noise eliminating the need for an external regulator. They insures stable high frequency operation at 3.0V through 5.5V supply voltage . VCO regulated voltage is used only for VCO. PLL regulated voltage is used for ECL-prescaler, CMOS-counter, internal logic circuits and crystal oscillator. All digital input / output pins are referenced to supply voltage rather than regulated voltage. CRYSTAL OSCILLATOR S1T8536 has a oscillator circuit composed of CMOS inverter amplifier. In case of inputting the external reference frequency directly, use OSCI terminal (Pin 13). .
OSCI
13
OSCO
12
OSCI
13
OSCO
12
external
LOOP FILTER Following figure shows third order passive loop filter
CP
7
VCO tuning
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S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
LOCK DETECTOR OPERATION
1/OSC fREF fPLL
1/(OSC / R)
CP LD
E High
When the situation that E(error) is less than one period of reference frequency, 1/OSC, continues more than three cycles of reference counter output, 1/(OSC/R), lock detector outputs `High'.
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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
PLL / VCO FUNCTIONAL DESCRIPTION
VOLTAGE CONTROLLED OSCILLATOR S1T8536's voltage controlled oscillator (VCO) uses a fully differential topology, with L-C resonant tank circuit offchip. Following figure shows external components for VCO operation.
LOOP FILTER 1 2 3
charge pump
REGULATOR
Following figure shows external components in case of using external VCO.
VCO 1 2 3
REGULATOR
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S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PROGRAMMING DESCRIPTION
SERIAL DATA PROGRAMMING TIMING Every bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable (LE) pin goes to high, stored data is latched according to the group code. The three terminals, CLK, DATA and LE, contain schmitt trigger circuits to keep the programming from errors caused by noise and etc.
>100 ns
CLK DATA LSB >50 ns >50 ns LE >50 ns >100 ns >50 ns LSB+1 LSB+2 MSB-2 MSB-1 MSB LSB
SERIAL DATA PROGRAMMING GROUP S1T8536 can be controlled through 3 kinds of program group. Each group is identified by selective 2 bits group codes given below. MSB-1 GC1 0 0 1 1 MSB GC0 0 1 0 1 Group Selection Control Latch N-Counter Latch R-Counter Latch Not Allowed
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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
PROGRAMMING DESCRIPTION CONTROL DATA PROGRAMMING (Data should be shifted in LSB first)
LSB D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 G1
MSB ` G0
control data
group-code 00
Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Name PDP CPI CPZ RXPD TXPD VCOPD PLLPD OSCPD TEST0 TEST1
Description Phase detector polarity select. Charge pump output current select. Charge pump output state select. Receiver power down control. Transmitter power down control. VCO power down control. PLL power down control. Crystal oscillator power down control Test mode control. Test mode control.
Setting to `0' Negative VCO + 1.5mA Normal operation Receiver `ON' Transmitter 'ON' VCO `ON' PLL `ON' Oscillator `ON' See below.
Setting to `1' Positive VCO + 4.5mA High Impedance Receiver `OFF' Transmitter `OFF' VCO `OFF' PLL `OFF' Oscillator `OFF'
Charge Pump Polarity Depending upon VCO characteristics, phase detector polarity should be set accordingly. When VCO characteristics are like (1), phase detector polarity bit (PDP) should be set low (`0'). When VCO characteristics are like (2), phase detector polarity bit (PDP) should be set high (`1').
VCO Frequency (2) positive
(1) negative VCO Tuning Voltage
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S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PROGRAMMING DESCRIPTION
Charge Pump Output State Control CPZ bit is provided for open loop modulation during TX time slot in TDD (Time Division Duplex) system. D2 CPZ 0 1 Power Mode Control D3 RX PD 0 1 1 1 1 1 D4 TX PD 1 0 1 1 1 1 D5 VCO PD 0 0 0 0 1 1 D6 PLL PD 0 0 0 1 1 1 D7 OSC PD 0 0 0 0 0 1 Frequency Doubler ON ON OFF OFF OFF OFF VCO Regulator ON ON ON ON OFF OFF Power down state PLL Regulator ON ON ON ON ON OFF RX Regulator ON OFF OFF OFF OFF OFF TX Regulator OFF ON OFF OFF OFF OFF Charge pump output state Normal High impedance VCO operation Closed loop Open Loop
Test Mode Control
D9 TEST1 0 0 1 1
D8 TEST0 0 1 0 1
LD Output Lock Detect fPLL (VCO / N) fREF (OSC / R) High
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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
PROGRAMMING DESCRIPTION
N-COUNTER DIVISION RATIO DATA PROGRAMMING (Data should be shifted in LSB first) The N-counter consists of the 5-bit swallow counter (A-counter), 8-bit programmable main counter (B-counter) and dual-modulus prescaler providing 32 / 33 division.
LSB A0 A1 A2 A3 A4 B0 B1 B2 B3 B4 B5 ` B6 B7 G1
MSB G0
Swallow-counter (A-counter)
Main-counter (B-counter) group-code 10
5-Bit Swallow Counter (A-Counter) Division Ratio A = A4*2^4 + A3*2^3 + A2*2^2 + A1*2^1 + A0*2^0 Division ratio : 0 to 31, A < B Division Ratio (A-Counter) 0 1 * 31 A4 0 1 * 1 A3 0 0 * 1 A2 0 0 * 1 A1 0 0 * 1 A0 0 0 * 1
8-Bit Main Counter (B-Counter) Division Ratio B = B7*2^7 + B6*2^6 + B5*2^5 + B4*2^4 + B3*2^3 + B2*2^2 + B1*2^1 + B0*2^0 Division ratio : 3 to 255, B > A Division Ratio (B-Counter) 3 4 * 255 N-Counter Division Ratio N = (PXB) + A P : Modulus of dual modulus prescaler which is 32 B : Division ratio of 8-bit main counter A : Division ratio of 5-bit swallow counter B7 1 0 * 1 B6 1 0 * 1 B5 0 1 * 1 B4 0 0 * 1 B3 0 0 * 1 B2 0 0 * 1 B1 0 0 * 1 B0 0 0 * 1
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S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PROGRAMMING DESCRIPTION
REFERENCE-COUNTER DIVISION RATIO DATA PROGRAMMING (Data should be shifted in LSB first) The R-counter consists of the 6-bit reference counter.
LSB R0 R1 R2 R3 R4 R5 G1
MSB G0
R-counter
group-code 01
6-Bit Reference Counter Division Ratio R = R5*2^5 + R4*2^4 + R3*2^3 + R2*2^2 + R1*2^1 + R0*2^0 Division ratio : 3 to 63
Division Ratio 3 4 * 63
R5 1 0 * 1
R4 1 0 * 1
R3 0 1 * 1
R2 0 0 * 1
R1 0 0 * 1
R0 0 0 * 1
Example) If a 19.2MHz oscillator is connected, the internal PLL reference frequency is 400KHz,and the VCO frequency is 1.2GHz,then equation is as follows. R = X-tal / Reference Frequency R = 19.2MHz / 400KHz = 48(d) = 110000(b) The R register setting is 00001101(b). N = Fvco / Freference N =1.2GHz / 400KHz = 3000 N = 3000 / 32 = 93.75 , S = 0.75 * 32 = 24 , The B(main counter) is 93(d) = 1011101(b) The S(swallow counter) is 24(d) = 11000(b)
The N register setting is 000111011101010(b).
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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
TEST CIRCUIT
C43 4.7p
C42 47p
L6 270nH
L5 270nH C40 C41 7p 7p C39 0.5p
SAFU110.6MSA40T 10 9 8 7 6 VCC 1 2 3 4 5 C35 27p C36 0.5p C34 27p L3 56n 28 27 26 25 C31 22p VC1 10p VCC VCC R22 33 C32 47p C33 4.7p
VCC R23 18 C49 47p C44 4.7p MOP 36
C38 4.7n
C37 47p
R21 470nH 18
35
34
33
32
31
30
29
IFN
GNDIF
GNDIF
IFP
GNDQUAD
VCCQUAD
VCCMIX
VCCMIX
QUADIN
VCCIF
MON
R25 22 24 23 R18 11k R19 C30 15k 12p R15 0 C26 15n 18 17 R14 12k R3 220 C24 47p C25 4.7n R17 33k C27 47p R16 33k C28 4.7n
37 C47 10n SMA C46 47p C49 1.2p C48 C61 1.5p 38 39 40 41 42
VREGRX GNDMIX GNDMIX MIP MIN GNDFD
GNDBB
QUADOUT
22 BUFIN C25 8p 21 BUFOUT DSINP DSINN 20 19
C51 4.7p
C50 47p VCC R24 18 C55 4.7p C54 47p C56 C57 N.C 0.5p
43 VREGTX C53 10n C52 47p 44 45 L7 660nH GNDFD VCCFD
S1T8536X01
SHO DSOUT
SHEN 16 RSSI 1 VREGVCO VREGPLL CE OSCO DATA CLK OSCI 15 14 13 19.2MHz
C21 30pF C22 20pF R12 56k
TP2 C23 10n RSSI
46 TXOUT VCC R20 C59 47p 18 47 GNDVCO GNDPLL
SMA7
11
C1 10n
C2 47p
L1 R1 L2 R2 L2
330n 50 330n 50 330n C4 1n VCC R3 18 C5 100p C6 10n R6 C13 39p 1 2 3 4 5 C9 47p C10 4.7p 15k C14 560p C15 15n R7 1.2k C60 ? C7 47p
C8 10n
C16 47p C17 47p C18 47p
10
12
48 VCCVCO C52 4.7p
VCCPLL
VCON
VCOP
CP
LD
2
3
4
5
6
7
8
9
LE
R8 1K R9 1K R10 1K
JP1 1 2 3 4 5 6 7 CNT1 1 2 3 4 5 6 7 14 13 12 11 10 9 8
U2 VC0-1300GHz GND 12
VCC SW1 SW SPDT R4 1k C11 1n
GND
11 10 9 8 7 R5 3.9k C12 100n
GND GND VSW GND MOD
OUT GND VCC GND CONT
R11 5k
VCC C19 100p C20 10p
6
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S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
APPLICATION CIRCUIT
SAFU110.6MSA40T C43 4.7p C42 47p L6 270nH L5 270nH C40 C41 7p 7p C38 4.7n C37 47p C39 0.5p 10 9 8 7 6 VCC R21 18 1 2 3 4 5 C36 0.5p C35 27p 470nH L3 56n 30 29 28 27 26 25 C31 22p VC1 10p C34 27p VCC R22 33 C32 47p C33 4.7n
VCC R23 18 C49 47p C44 4.7p MOP 36
VCC R25 18
35
34
33
32
31
IFN
GNDIF
GNDIF
IFP
GNDQUAD
VCCQUAD
VCCMIX
VCCMIX
QUADIN
VCCIF
MON
37 VCC R34 100 R35 18k C3 10p L14 1.2nH L13 1.2nH C68 RFIN 100p RFIN L15 N.C TxVcc C57 10p L10 3.9nH TxOUT C62 L11 TxOUT 33p 2.2nH R31 100 R32 18k L9 N.C Q1 HPFB0420 SMA C11 200p C55 4.7p C56 C63 L8 N.C 5p Q2 HPFB0420 L12 N.C VCC R24 18 C54 47p C51 4.7p SMA C49 1p C61 C47 10n C46 47p C48 2.7p 38 39
24 23 R18 11k R19 C30 15k 12p R15 0 R14 12k C26 15n R3 220 C24 47p C25 4.7n R17 33k C27 47p R16 33k C28 4.7n
VREGRX GNDMIX GNDMIX
GNDBB
QUADOUT
40 MIP 41 42 MIN GNDFD
22 BUFIN C29 8p 21 BUFOUT DSINP DSINN 20 19 18 17
C50 47p
S1T8536X01
SHO DSOUT
43 VREGTX C53 10n C52 47p 44 45 L7 660nH GNDFD VCCFD
SHEN 16 RSSI 1 VREGVCO VREGPLL CE OSCO DATA CLK OSCI 15 14 13 19.2MHz
C21 30pF VC2 10p C22 10pF R12 56k
TP4 RxDATA C23 10n TP2 RSSI
46 TXOUT GNDPLL VCC R20 18 C59 47p 47 GNDVCO
CP
LD
11
C17 47p
LE
1.8p
R1 VC 1 - 3p C12 C26 2.2p R2 L1 2k 1nH C2 47p
10 HVC355B D2
DIODE
R4 10
VCC R3 18 C7 47p C6 10n R6 5.6k
R8 1K R9 1K R10 1K C16 47p
C4 2.2p
D1 L2 1nH 0 TP3 CP
C5 100p
C8 10n
10
VCO
100p
R31
12
C18 47p
48 VCCVCO C52 4.7p
2
3
4
5
VCCPLL
VCON
VCOP
6
7
8
9
JP1 LE DATA CLK LD GND MOD TxVcc 1 2 3 4 5 6 7 CNT1 14 13 12 11 10 9 8 AFO SHEN CE RXD GND RSSI RxVcc C19 100p
C1 103
VREGRX R28 C67 150p TP1 MOD R5 3.9k R27 68 4.7K R2 10k
C13 N.C
C14 680p
R7 4.7k C15 4.7n C60 ?
R11 5k
TxVcc C9 47p C10 4.7p
VCC C20 10n
24

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